The present invention relates in general to redundant signed digit (RSD) analog-to-digital converters and, more particularly, to a two stage cyclic analog-to-digital converter that exhibits a high degree of linearity by correctly determining the least significant bit.
In the past RSD analog-to-digital converters have been configured with an input track and hold and comparator circuit, followed by an RSD conversion stage. During a first clock phase, the track and hold and comparator circuit would acquire the voltage that was to be converted and compare the voltage to a high level reference voltage and to a low level reference voltage. The resulting logic signal would be stored in a serial storage register. During the following phase, the acquired voltage is processed by the RSD stage. A residue voltage, is generated in the RSD stage, that depends on the comparison results. The residue voltage is recycled through a feedback loop to the input of the track and hold and comparator circuit so as to repeat the conversion process until the remaining bits are determined. Thus, an n-bit RSD analog-to-digital converter requires n clock cycles to perform the n-bit conversion, and is thereby limited in conversion speed due to the large number of clock cycles required to complete a conversion.
Furthermore, present RSD analog-to-digital converters are subject to reduced linearity performance due to inaccurate determination of the least significant bit (lsb) of the conversion. If the voltage being compared for the lsb lies between the high and low level reference voltages, a linearity error is introduced in that the lsb must be forced into a logic high or logic low condition at the input to the storage register.
Hence, a need exists for a high-speed RSD analog-to-digital converter having a more accurately determined LSB.